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VLSID
2004
IEEE
117views VLSI» more  VLSID 2004»
14 years 9 months ago
Evaluating the Reliability of Defect-Tolerant Architectures for Nanotechnology with Probabilistic Model Checking
As we move from deep submicron technology to nanotechnology for device manufacture, the need for defect-tolerant architectures is gaining importance. This is because, at the nanos...
Gethin Norman, David Parker, Marta Z. Kwiatkowska,...
ICCD
2001
IEEE
106views Hardware» more  ICCD 2001»
14 years 6 months ago
Pre-routing Estimation of Shielding for RLC Signal Integrity
The formiila-based I<,JJ model is a figiire of merit for the inductive coirpling, and has been used to solve the simrrltaneoris shield insertion and net ordering (SINO) and sim...
James D. Z. Ma, Arvind Parihar, Lei He
ICCAD
2008
IEEE
147views Hardware» more  ICCAD 2008»
14 years 6 months ago
Overlay aware interconnect and timing variation modeling for double patterning technology
— As Double Patterning Technology (DPT) becomes the only solution for 32-nm lithography process, we need to investigate how DPT affects the performance of a chip. In this paper, ...
Jae-Seok Yang, David Z. Pan
ICCAD
2007
IEEE
143views Hardware» more  ICCAD 2007»
14 years 6 months ago
TIP-OPC: a new topological invariant paradigm for pixel based optical proximity correction
—As the 193nm lithography is likely to be used for 45nm and even 32nm processes, much more stringent requirement will be posed on Optical Proximity Correction (OPC) technologies....
Peng Yu, David Z. Pan
ICCAD
2006
IEEE
141views Hardware» more  ICCAD 2006»
14 years 6 months ago
An accurate sparse matrix based framework for statistical static timing analysis
Statistical Static Timing Analysis has received wide attention recently and emerged as a viable technique for manufacturability analysis. To be useful, however, it is important th...
Anand Ramalingam, Gi-Joon Nam, Ashish Kumar Singh,...