Sciweavers

48 search results - page 4 / 10
» The Validity of Retiming Sequential Circuits
Sort
View
ICCAD
2007
IEEE
109views Hardware» more  ICCAD 2007»
14 years 3 months ago
Inductive equivalence checking under retiming and resynthesis
Retiming and resynthesis are among the most important techniques for practical sequential circuit optimization. However, their applicability is much limited due to verification c...
Jie-Hong Roland Jiang, Wei-Lun Hung
DAC
1999
ACM
14 years 8 months ago
Simultaneous Circuit Partitioning/Clustering with Retiming for Performance Optimization
Partitioning and clustering are crucial steps in circuit layout for handling large scale designs enabled by the deep submicron technologies. Retiming is an important sequential lo...
Jason Cong, Honching Li, Chang Wu
ICCAD
1998
IEEE
80views Hardware» more  ICCAD 1998»
13 years 11 months ago
On the optimization power of retiming and resynthesis transformations
Retiming and resynthesis transformations can be used for optimizing the area, power, and delay of sequential circuits. Even though this technique has been known for more than a de...
Rajeev K. Ranjan, Vigyan Singhal, Fabio Somenzi, R...
ICCAD
1999
IEEE
90views Hardware» more  ICCAD 1999»
13 years 11 months ago
Marsh: min-area retiming with setup and hold constraints
This paper describes a polynomial time algorithm for min-area retiming for edge-triggered circuits to handle both setup and hold constraints. Given a circuit G and a target clock ...
Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K...
ICCAD
2007
IEEE
113views Hardware» more  ICCAD 2007»
14 years 3 months ago
Combinational and sequential mapping with priority cuts
An algorithm for technology mapping of combinational and sequential logic networks is proposed and applied to mapping into K-input lookup-tables (K-LUTs). The new algorithm avoids...
Alan Mishchenko, Sungmin Cho, Satrajit Chatterjee,...