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ISCA
1996
IEEE
99views Hardware» more  ISCA 1996»
15 years 9 months ago
High-Bandwidth Address Translation for Multiple-Issue Processors
In an effort to push the envelope of system performance, microprocessor designs are continually exploiting higher levels of instruction-level parallelism, resulting in increasing ...
Todd M. Austin, Gurindar S. Sohi
ISPASS
2009
IEEE
16 years 12 days ago
GARNET: A detailed on-chip network model inside a full-system simulator
Until very recently, microprocessor designs were computation-centric. On-chip communication was frequently ignored. This was because of fast, single-cycle on-chip communication. T...
Niket Agarwal, Tushar Krishna, Li-Shiuan Peh, Nira...
150
Voted
ISCA
2009
IEEE
148views Hardware» more  ISCA 2009»
16 years 7 days ago
Disaggregated memory for expansion and sharing in blade servers
Analysis of technology and application trends reveals a growing imbalance in the peak compute-to-memory-capacity ratio for future servers. At the same time, the fraction contribut...
Kevin T. Lim, Jichuan Chang, Trevor N. Mudge, Part...
VISUALIZATION
1992
IEEE
15 years 9 months ago
Display of Scientific Data Structures for Algorithm Visualization
algorithms as networks of modules. The data flow architecture is popular because of the flexibility of mixing calculation modules with display modules, and because of its easy grap...
William L. Hibbard, Charles R. Dyer, Brian E. Paul
TPDS
2002
142views more  TPDS 2002»
15 years 5 months ago
MediaWorm: A QoS Capable Router Architecture for Clusters
With the increasing use of clusters in real-time applications, it has become essential to design high performance networks with Quality-of-ServiceQoS guarantees. In this paper, we...
Ki Hwan Yum, Eun Jung Kim, Chita R. Das, Aniruddha...