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PREMI
2005
Springer
14 years 27 days ago
Artificial Neural Network Engine: Parallel and Parameterized Architecture Implemented in FPGA
In this paper we present and analyze an artificial neural network hardware engine, its architecture and implementation. The engine was designed to solve performance problems of the...
Milene Barbosa Carvalho, Alexandre Marques Amaral,...
FCCM
1998
IEEE
170views VLSI» more  FCCM 1998»
13 years 11 months ago
Characterization and Parameterization of a Pipeline Reconfigurable FPGA
ended abstract defines a class of architectures for pipeline reconfigurable FPGAs by parameterizing a generic model. This class of architectures is sufficiently general to allow e...
Matthew Moe, Herman Schmit, Seth Copen Goldstein
DATE
2000
IEEE
139views Hardware» more  DATE 2000»
13 years 12 months ago
Target Architecture Oriented High-Level Synthesis for Multi-FPGA Based Emulation
This paper presents a new approach on combined highlevel synthesis and partitioning for FPGA-based multi-chip emulation systems. The goal is to synthesize a prototype with maximal...
Oliver Bringmann, Wolfgang Rosenstiel, Carsten Men...
CDES
2006
87views Hardware» more  CDES 2006»
13 years 8 months ago
A Configuration Concept for a Massively Parallel FPGA Architecture
Sandeep Kumar, Christof Paar, Jan Pelzl, Gerd Pfei...