During the last years, several logic styles that counteract side-channel attacks have been proposed. They all have in common that their level of resistance heavily depends on imple...
This paper introduces a CAD framework for co-simulation of hybrid circuits containing CMOS and SET (Single Electron Transistor) devices. An improved analytical model for SET is al...
- In this paper, we propose an auto-companding technique for the analog behavioral modeling via wavelet collocation method. The companding function is automatically constructed acc...
Jian Wang, Jun Tao, Xuan Zeng, Charles Chiang, Dia...
— Direct tunneling current is the major component of static power dissipation of a CMOS circuit for technology below 65nm, where the gate dielectric (SiO2) is very low. We intuit...
Saraju P. Mohanty, Ramakrishna Velagapudi, Valmiki...
We present a technique for synthesizing power- as well as area-optimized circuits from hierarchical data flow graphs under throughput constraints. We allow for the use of complex...