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ISLPED
1995
ACM
129views Hardware» more  ISLPED 1995»
13 years 11 months ago
CMOS dynamic power estimation based on collapsible current source transistor modeling
When estimating the dynamic power dissipated by a circuit di erent methods ranging from numeric analog simulation to event-driven logic simulation have been proposed. However, as ...
Abelardo Pardo, R. Iris Bahar, Srilatha Manne, Pet...
CDC
2010
IEEE
100views Control Systems» more  CDC 2010»
13 years 2 months ago
A resistance-based approach to consensus algorithm performance analysis
Abstract-We study the well known linear consensus algorithm by means of a LQ-type performance cost. We want to understand how the communication topology influences this algorithm. ...
Federica Garin, Enrico Lovisari, Sandro Zampieri
ICCAD
2003
IEEE
115views Hardware» more  ICCAD 2003»
14 years 4 months ago
Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits
This paper presents an efficient method for verifying hazard freedom in timed asynchronous circuits. Timed circuits are a class of asynchronous circuits that utilize explicit tim...
Curtis A. Nelson, Chris J. Myers, Tomohiro Yoneda
ICCD
2005
IEEE
128views Hardware» more  ICCD 2005»
14 years 4 months ago
Automatic Synthesis of Composable Sequential Quantum Boolean Circuits
This paper presents a methodology to transfer self-timed circuit specifications into sequential quantum Boolean circuits (SQBCs) and composable SQBCs (CQBCs). State graphs (SGs) a...
Li-Kai Chang, Fu-Chiung Cheng
ITC
1997
IEEE
129views Hardware» more  ITC 1997»
13 years 11 months ago
On Using Machine Learning for Logic BIST
This paper presents a new approach for designing test sequences to be generated on–chip. The proposed technique is based on machine learning, and provides a way to generate effi...
Christophe Fagot, Patrick Girard, Christian Landra...