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DATE
2008
IEEE
121views Hardware» more  DATE 2008»
14 years 2 months ago
A Bridging Fault Model Where Undetectable Faults Imply Logic Redundancy
We define a robust fault model as a model where the existence of an undetectable fault implies the existence of logic redundancy, or more generally, a suboptimality in the synthe...
Irith Pomeranz, Sudhakar M. Reddy
CIRA
2007
IEEE
177views Robotics» more  CIRA 2007»
14 years 2 months ago
Robotic Self-Replication in a Structured Environment without Computer Control
— The ability to self-replicate is one of the distinctive features of living organisms. Robots capable of self-replication would have a profound impact on the field of robotics ...
Steven Eno, Lauren Mace, Jianyi Liu, Brian Benson,...
DATE
2007
IEEE
83views Hardware» more  DATE 2007»
14 years 2 months ago
High-level test synthesis for delay fault testability
A high-level test synthesis (HLTS) method targeted for delay fault testability is presented. The proposed method, when combined with hierarchical test pattern generation for embed...
Sying-Jyan Wang, Tung-Hua Yeh
IPPS
2007
IEEE
14 years 2 months ago
Speedup using Flowpaths for a Finite Difference Solution of a 3D Parabolic PDE
Partial differential equations (PDEs) are used to model physical phenomena and then appropriate convergent numerical algorithms are employed to solve them and create computer simu...
Darrin M. Hanna, Anna M. Spagnuolo, Michael DuChen...
ISVLSI
2007
IEEE
204views VLSI» more  ISVLSI 2007»
14 years 2 months ago
Designing Memory Subsystems Resilient to Process Variations
As technology scales, more sophisticated fabrication processes cause variations in many different parameters in the device. These variations could severely affect the performance ...
Mahmoud Ben Naser, Yao Guo, Csaba Andras Moritz