The Y-architecture for on-chip interconnect is based on pervasive use of 0-, 120-, and 240-degree oriented semi-global and global wiring. Its use of three uniform directions explo...
Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Io...
This paper presents a new Multilevel hierarchical FPGA (MFPGA) architecture that unifies two unidirectional programmable networks: A predictible downward network based on the But...
Hayder Mrabet, Zied Marrakchi, Pierre Souillot, Ha...
Abstract. Nowadays, power consumption reduction techniques are being increasingly used in computer systems, and high-performance computing systems are not an exception. In particul...
Marina Alonso, Salvador Coll, Vicente Santonja, Ju...
How does multilevel metalization impact the design of FPGA interconnect? The availability of a growing number of metal layers presents the opportunity to use wiring in the thirddi...
The problem of interconnect architecture arises when an array of processors needs to be integrated on one chip. With the deep sub-micron technology, devices become cheap while wir...
Feng Zhou, Esther Y. Cheng, Bo Yao, Chung-Kuan Che...