Lowering supply voltage is one of the most effective techniques for reducing microprocessor power consumption. Unfortunately, at low voltages, chips are very sensitive to process ...
Timothy N. Miller, Xiang Pan, Renji Thomas, Naser ...
In this work, we report on an unprecedented design where digital, analog, and MEMS technologies are combined to realize a generalpurpose single-chip CMOS microsystem. The converge...
Robert M. Senger, Eric D. Marsman, Michael S. McCo...
Leakage power is a major concern in current and future microprocessor designs. In this paper, we explore the potential of architectural techniques to reduce leakage through power-...
Two new FPGA designs for the Advanced Encryption Standard (AES) are presented. The first is believed to be the fastest, achieving 25 Gbps throughput using a Xilinx Spartan-III (XC3...
We present a technique for fast estimation of the power consumed by the cache and bus sub-system of a parameterized system-on-a-chip design for a given application. The technique ...