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» The design of a high performance low power microprocessor
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ISLPED
2010
ACM
158views Hardware» more  ISLPED 2010»
13 years 9 months ago
Temperature- and energy-constrained scheduling in multitasking systems: a model checking approach
The ongoing scaling of semiconductor technology is causing severe increase of on-chip power density and temperature in microprocessors. This has raised urgent requirement for both...
Weixun Wang, Xiaoke Qin, Prabhat Mishra
VLSID
2009
IEEE
108views VLSI» more  VLSID 2009»
14 years 9 months ago
Metric Based Multi-Timescale Control for Reducing Power in Embedded Systems
Abstract--Digital control for embedded systems often requires low-power, hard real-time computation to satisfy high control-loop bandwidth, low latency, and low-power requirements....
Forrest Brewer, João Pedro Hespanha, Nitin ...
ISQED
2006
IEEE
101views Hardware» more  ISQED 2006»
14 years 3 months ago
Compiler-Directed Power Density Reduction in NoC-Based Multi-Core Designs
As transistor counts keep increasing and clock frequencies rise, high power consumption is becoming one of the most important obstacles, preventing further scaling and performance...
Sri Hari Krishna Narayanan, Mahmut T. Kandemir, Oz...
VLSID
2006
IEEE
134views VLSI» more  VLSID 2006»
14 years 9 months ago
ADC Precision Requirement for Digital Ultra-Wideband Receivers with Sublinear Front-Ends: A Power and Performance Perspective
This paper presents the power and performance analysis of a digital, direct sequence ultra-wideband (DS-UWB) receiver operating in the 3 to 4 GHz band. The signal to noise and dis...
Ivan Siu-Chuang Lu, Neil Weste, Sri Parameswaran
VLSI
2010
Springer
13 years 6 months ago
Trends and techniques for energy efficient architectures
Abstract--Microprocessor architectures have become increasingly power limited in recent years. Currently power and thermal envelopes dictate peak performance limits more than any o...
Victor Jimenez, Roberto Gioiosa, Eren Kursun, Fran...