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» The design of a high performance low power microprocessor
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DAC
2004
ACM
14 years 15 days ago
Leakage in nano-scale technologies: mechanisms, impact and design considerations
The high leakage current in nano-meter regimes is becoming a significant portion of power dissipation in CMOS circuits as threshold voltage, channel length, and gate oxide thickne...
Amit Agarwal, Chris H. Kim, Saibal Mukhopadhyay, K...
HIPEAC
2009
Springer
14 years 3 months ago
Hybrid Super/Subthreshold Design of a Low Power Scalable-Throughput FFT Architecture
In this article, we present a parallel implementation of a 1024 point Fast Fourier Transform (FFT) operating with a subthreshold supply voltage, which is below the voltage that tur...
Michael B. Henry, Leyla Nazhandali
SBACPAD
2006
IEEE
147views Hardware» more  SBACPAD 2006»
14 years 2 months ago
Controlling the Power and Area of Neural Branch Predictors for Practical Implementation in High-Performance Processors
Neural-inspired branch predictors achieve very low branch misprediction rates. However, previously proposed implementations have a variety of characteristics that make them challe...
Daniel A. Jiménez, Gabriel H. Loh
TCAD
2011
13 years 3 months ago
Low-Power Clock Tree Design for Pre-Bond Testing of 3-D Stacked ICs
—Pre-bond testing of 3-D stacked integrated circuits (ICs) involves testing each individual die before bonding. The overall yield of 3-D ICs improves with pre-bond testability be...
Xin Zhao, Dean L. Lewis, Hsien-Hsin S. Lee, Sung K...
ISCAS
2006
IEEE
113views Hardware» more  ISCAS 2006»
14 years 2 months ago
Low power state-parallel relaxed adaptive Viterbi decoder design and implementation
Abstract— In this paper, we present an algorithm/architecturelevel design solution for implementing state-parallel adaptive Viterbi decoders that, compared with their Viterbi cou...
Fei Sun, Tong Zhang