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» The design of a high performance low power microprocessor
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GLVLSI
2008
IEEE
190views VLSI» more  GLVLSI 2008»
14 years 3 months ago
A low leakage 9t sram cell for ultra-low power operation
This paper presents the design and evaluation of a new SRAM cell made of nine transistors (9T). The proposed 9T cell utilizes a scheme with separate read and write wordlines; it i...
Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi
ISLPED
2007
ACM
94views Hardware» more  ISLPED 2007»
13 years 10 months ago
Design of an efficient power delivery network in an soc to enable dynamic power management
Dynamic voltage scaling (DVS) is known to be one of the most efficient techniques for power reduction of integrated circuits. Efficient low voltage DC-DC conversion is a key enabl...
Behnam Amelifard, Massoud Pedram
OSDI
2002
ACM
14 years 9 months ago
Vertigo: Automatic Performance-Setting for Linux
Combining high performance with low power consumption is becoming one of the primary objectives of processor designs. Instead of relying just on sleep mode for conserving power, a...
Krisztián Flautner, Trevor N. Mudge
CORR
2008
Springer
57views Education» more  CORR 2008»
13 years 9 months ago
Square Complex Orthogonal Designs with Low PAPR and Signaling Complexity
Abstract--Space-Time Block Codes from square complex orthogonal designs (SCOD) have been extensively studied and most of the existing SCODs contain large number of zero. The zeros ...
Smarajit Das, B. Sundar Rajan
SBCCI
2005
ACM
185views VLSI» more  SBCCI 2005»
14 years 2 months ago
Automatic generation of test sets for SBST of microprocessor IP cores
Higher integration densities, smaller feature lengths, and other technology advances, as well as architectural evolution, have made microprocessor cores exceptionally complex. Cur...
Ernesto Sánchez, Matteo Sonza Reorda, Giova...