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» The design of a high performance low power microprocessor
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ISCA
1996
IEEE
99views Hardware» more  ISCA 1996»
14 years 1 months ago
High-Bandwidth Address Translation for Multiple-Issue Processors
In an effort to push the envelope of system performance, microprocessor designs are continually exploiting higher levels of instruction-level parallelism, resulting in increasing ...
Todd M. Austin, Gurindar S. Sohi
DAC
2001
ACM
14 years 9 months ago
Power-Aware Scheduling under Timing Constraints for Mission-Critical Embedded Systems
Power-aware systems are those that must make the best use of available power. They subsume traditional low-power systems in that they must not only minimize power when the budget ...
Jinfeng Liu, Pai H. Chou, Nader Bagherzadeh, Fadi ...
VLSID
2007
IEEE
99views VLSI» more  VLSID 2007»
14 years 9 months ago
Low Power Implementation for Minimum Norm Sorting and Block Upper Tri-angularization of Matrices used in MIMO Wireless Systems
Multiple Input - Multiple Output (MIMO) wireless technology involves highly complex vectors and matrix computations which are directly related to increased power and area consumpt...
Zahid Khan, Tughrul Arslan, John S. Thompson, Ahme...
ISLPED
2003
ACM
113views Hardware» more  ISLPED 2003»
14 years 2 months ago
Reducing power density through activity migration
Power dissipation is unevenly distributed in modern microprocessors leading to localized hot spots with significantly greater die temperature than surrounding cooler regions. Exc...
Seongmoo Heo, Kenneth C. Barr, Krste Asanovic
FPL
2008
Springer
116views Hardware» more  FPL 2008»
13 years 10 months ago
NOC architecture design for multi-cluster chips
For the next generation of multi-core processors, the onchip interconnection networks must be efficient to achieve high data throughput and performance. Moreover, these interconne...
Henrique C. Freitas, Philippe Olivier Alexandre Na...