517 search results - page 14 / 104 » The design of a low energy FPGA |
CODES
2004
IEEE
13 years 11 months ago
2004
IEEE
Future embedded and wireless devices will be increasingly powerful supporting many applications including one of the most crucial, security. Although many wireless and embedded de...
ICCD
2004
IEEE
14 years 4 months ago
2004
IEEE
Existing schemes for cache energy optimization incorporate a limited degree of dynamic associativity: either direct mapped or full available associativity (say 4-way). In this pap...
ICCD
2001
IEEE
14 years 4 months ago
2001
IEEE
This paper deals with low-energy code generation for a highly optimized digital signal processor designed for mobile communication applications. We present a genetic algorithm bas...
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Voted
ISLPED
1999
ACM
13 years 11 months ago
1999
ACM
This paper describes a new mixed-swing topology for dual-rail domino logic that results in a simultaneous energy and delay reduction. HSPICE simulation results for a 1-bit full ad...
ISLPED
1999
ACM
13 years 11 months ago
1999
ACM
—Energy-efficient design of battery-powered systems demands optimizations in both hardware and software. We present a modular approach for enhancing instruction level simulators ...