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» The energy complexity of register files
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CODES
2001
IEEE
13 years 11 months ago
Evaluating register file size in ASIP design
Interest in synthesis of Application Specific Instruction Set Processors or ASIPs has increased considerably and a number of methodologies have been proposed for ASIP design. A ke...
Manoj Kumar Jain, Lars Wehmeyer, Stefan Steinke, P...
CDES
2006
74views Hardware» more  CDES 2006»
13 years 9 months ago
Zero Detect-Based Low Power Registers File Access
- With the intention of reduce significantly the energy that wastes away when having a read or write access to the register file, since the technique Zero Detect diminishes the tra...
Moises Zarate, Oscar Camacho Nieto, Luis A. Villa ...
DATE
2004
IEEE
114views Hardware» more  DATE 2004»
13 years 11 months ago
Power Aware Variable Partitioning and Instruction Scheduling for Multiple Memory Banks
Many high-end DSP processors employ both multiple memory banks and heterogeneous register files to improve performance and power consumption. The complexity of such architectures ...
Zhong Wang, Xiaobo Sharon Hu
APCSAC
2003
IEEE
14 years 26 days ago
Reducing Access Count to Register-Files through Operand Reuse
This paper proposes an approach for reducing access count to register-files based on operand data reuse. The key idea is to compare source and destination operands of the current ...
Hiroshi Takamura, Koji Inoue, Vasily G. Moshnyaga
LCTRTS
2007
Springer
14 years 1 months ago
Addressing instruction fetch bottlenecks by using an instruction register file
The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by ...
Stephen Roderick Hines, Gary S. Tyson, David B. Wh...