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MICRO
2007
IEEE
144views Hardware» more  MICRO 2007»
14 years 3 months ago
Process Variation Tolerant 3T1D-Based Cache Architectures
Process variations will greatly impact the stability, leakage power consumption, and performance of future microprocessors. These variations are especially detrimental to 6T SRAM ...
Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David Bro...
MICRO
2007
IEEE
128views Hardware» more  MICRO 2007»
14 years 3 months ago
A Framework for Providing Quality of Service in Chip Multi-Processors
The trends in enterprise IT toward service-oriented computing, server consolidation, and virtual computing point to a future in which workloads are becoming increasingly diverse i...
Fei Guo, Yan Solihin, Li Zhao, Ravishankar Iyer
VTC
2007
IEEE
161views Communications» more  VTC 2007»
14 years 3 months ago
Early Results on Hydra: A Flexible MAC/PHY Multihop Testbed
— Hydra is a flexible wireless network testbed being developed at UT Austin. Our focus is networks that support multiple wireless hops and where the network, especially the MAC,...
Ketan Mandke, Soon-Hyeok Choi, Gibeom Kim, Robert ...
ATAL
2007
Springer
14 years 3 months ago
Scaling-up shopbots: a dynamic allocation-based approach
In this paper we consider the problem of eCommerce comparison shopping agents (shopbots) that are limited by capacity constraints. In light of the phenomenal increase both in dema...
David Sarne, Sarit Kraus, Takayuki Ito
DATE
2006
IEEE
123views Hardware» more  DATE 2006»
14 years 3 months ago
Networks on chips for high-end consumer-electronics TV system architectures
Consumer electronics products, such as high-end (digital) TVs, contain complex systems on chip (SOC) that offer high computational performance at low cost. Traditionally, these SO...
Frits Steenhof, Harry Duque, Björn Nilsson, K...