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ICCAD
2006
IEEE
125views Hardware» more  ICCAD 2006»
14 years 7 months ago
Performances improvement of FPGA using novel multilevel hierarchical interconnection structure
This paper presents a new Multilevel hierarchical FPGA (MFPGA) architecture that unifies two unidirectional programmable networks: A predictible downward network based on the But...
Hayder Mrabet, Zied Marrakchi, Pierre Souillot, Ha...
DATE
2009
IEEE
122views Hardware» more  DATE 2009»
14 years 5 months ago
A hybrid packet-circuit switched on-chip network based on SDM
—In this paper, we propose a novel on-chip communication scheme by dividing the resources of a traditional packet-switched network-on-chip between a packet-switched and a circuit...
Mehdi Modarressi, Hamid Sarbazi-Azad, Mohammad Arj...
ISCAS
2007
IEEE
128views Hardware» more  ISCAS 2007»
14 years 5 months ago
Collaborative Routing Architecture for FPGA
— In this paper we present the Collaborative Routing Architecture (CRA), a routing architecture specially designed to achieve high efficiency in hardware and competitive delay p...
Yaling Ma, Mingjie Lin
PPSN
1998
Springer
14 years 3 months ago
Ant Colonies for Adaptive Routing in Packet-Switched Communications Networks
In this paper we present AntNet, a novel adaptive approach to routing tables learning in packet-switched communications networks. AntNet is inspired by the stigmergy model of commu...
Gianni Di Caro, Marco Dorigo
ICCAD
1996
IEEE
140views Hardware» more  ICCAD 1996»
14 years 2 months ago
Register-transfer level estimation techniques for switching activity and power consumption
We present techniques for estimating switching activity and power consumption in register-transfer level (RTL) circuits. Previous work on this topic has ignored the presence of gl...
Anand Raghunathan, Sujit Dey, Niraj K. Jha