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» The performance of circuit switching in the internet
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INFOCOM
1998
IEEE
14 years 3 months ago
Implementing Distributed Packet Fair Queueing in a Scalable Switch Architecture
To support the Internet's explosive growth and expansion into a true integrated services network, there is a need for cost-effective switching technologies that can simultaneo...
Donpaul C. Stephens, Hui Zhang
ARVLSI
1995
IEEE
220views VLSI» more  ARVLSI 1995»
14 years 2 months ago
Optimization of combinational and sequential logic circuits for low power using precomputation
Precomputation is a recently proposed logic optimization technique which selectively disables the inputs of a sequential logic circuit, thereby reducing switching activity and pow...
José Monteiro, John Rinderknecht, Srinivas ...
3DIC
2009
IEEE
279views Hardware» more  3DIC 2009»
14 years 5 months ago
Compact modelling of Through-Silicon Vias (TSVs) in three-dimensional (3-D) integrated circuits
Abstract—Modeling parasitic parameters of Through-SiliconVia (TSV) structures is essential in exploring electrical characteristics such as delay and signal integrity (SI) of circ...
Roshan Weerasekera, Matt Grange, Dinesh Pamunuwa, ...
ICCAD
1998
IEEE
94views Hardware» more  ICCAD 1998»
14 years 3 months ago
Noise considerations in circuit optimization
Noise can cause digital circuits to switch incorrectly and thus produce spurious results. Noise can also have adverse power, timing and reliability e ects. Dynamic logic is partic...
Andrew R. Conn, Ruud A. Haring, Chandramouli Viswe...
DELTA
2006
IEEE
14 years 4 months ago
A Hardware Implementation of Layer 2 MPLS
This paper presents a hardware architecture for layer 2 Multi Protocol Label Switching (MPLS). MPLS is a protocol framework used primarily to prioritize internet traffic and impro...
Raymond Peterkin, Dan Ionescu