431 search results - page 26 / 87 » The predictability of branches in libraries |
ICCD
2002
IEEE
14 years 4 months ago
2002
IEEE
VLIW processors are statically scheduled processors and their performance depends on the quality of the compiler’s scheduler. We propose a scheduling scheme where the applicatio...
ARCS
2010
Springer
14 years 11 days ago
2010
Springer
Register renaming is a widely used technique to remove false data dependencies in contemporary superscalar microprocessors. The register rename logic includes a mapping table that ...
ISCA
1999
IEEE
13 years 12 months ago
1999
IEEE
Current work in Simultaneous Multithreading provides little benefit to programs that aren't partitioned into threads. We propose Simultaneous Subordinate Microthreading (SSMT...
HPCA
2008
IEEE
14 years 8 months ago
2008
IEEE
Hard-to-predict branches depending on longlatency cache-misses have been recognized as a major performance obstacle for modern microprocessors. With the widening speed gap between...
SBACPAD
2006
IEEE
14 years 1 months ago
2006
IEEE
Neural-inspired branch predictors achieve very low branch misprediction rates. However, previously proposed implementations have a variety of characteristics that make them challe...