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ISMVL
2010
IEEE
156views Hardware» more  ISMVL 2010»
15 years 7 months ago
Floating-Point Numeric Function Generators Based on Piecewise-Split EVMDDs
This paper proposes a new architecture for memorybased floating-point numeric function generators (NFGs). The design method uses piecewise-split edge-valued multivalued decision ...
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
96
Voted
ISMVL
1997
IEEE
82views Hardware» more  ISMVL 1997»
15 years 6 months ago
Finding Composition Trees for Multiple-Valued Functions
The composition tree of a given function, when it exists, provides a representation of the function revealing all possible disjunctive decompositions, thereby suggesting a realiza...
Elena Dubrova, Jon C. Muzio, Bernhard von Stengel
104
Voted
DAC
2004
ACM
16 years 3 months ago
A method to decompose multiple-output logic functions
This paper shows a method to decompose a given multipleoutput circuit into two circuits with intermediate outputs. We use a BDD for characteristic function (BDD for CF) to represe...
Tsutomu Sasao, Munehiro Matsuura
120
Voted
FPL
2005
Springer
107views Hardware» more  FPL 2005»
15 years 8 months ago
Programmable Numerical Function Generators: Architectures and Synthesis Method
This paper presents an architecture and a synthesis method for programmable numerical function generators of trigonometric functions, logarithm functions, square root, reciprocal,...
Tsutomu Sasao, Shinobu Nagayama, Jon T. Butler
102
Voted
ICCAD
2008
IEEE
117views Hardware» more  ICCAD 2008»
15 years 11 months ago
On the numbers of variables to represent sparse logic functions
— In an incompletely specified function f, don’t care values can be chosen to minimize the number of variables to represent f. It is shown that, in incompletely specified fun...
Tsutomu Sasao