48 search results - page 6 / 10 » The synthesis of combinational logic to generate probabiliti... |
TCAD
1998
13 years 7 months ago
1998
Abstract—We examine the implications of a new hazard-free combinational logic synthesis method [1], which generates multiplexor-based networks from binary decision diagrams (BDDs...
DDECS
2007
IEEE
14 years 1 months ago
2007
IEEE
- As shown by previous studies, shorts between the interconnect wires should be considered as the predominant cause of failures in CMOS circuits. Fault models and tools for targeti...
ICST
2008
IEEE
14 years 1 months ago
2008
IEEE
Testing remains a major challenge for model transformation development. Test models that are used as test data for model transformations, are constrained by various sources of kno...
ICCAD
2002
IEEE
14 years 4 months ago
2002
IEEE
In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV...
ACSD
2010
IEEE
13 years 5 months ago
2010
IEEE
Self-timed circuits present an attractive solution to the problem of process variation. However, implementing selftimed combinational logic can be complex and expensive. This pape...