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» The synthesis of cyclic combinational circuits
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DAC
2008
ACM
13 years 9 months ago
Leakage power-aware clock skew scheduling: converting stolen time into leakage power reduction
Clock skew scheduling has been traditionally considered as a tool for improving the clock period in a sequential circuit. Timing slack is "stolen" from fast combinationa...
Min Ni, Seda Ogrenci Memik
DAC
2007
ACM
14 years 8 months ago
Global Critical Path: A Tool for System-Level Timing Analysis
An effective method for focusing optimization effort on the most important parts of a design is to examine those elements on the critical path. Traditionally, the critical path is...
Girish Venkataramani, Mihai Budiu, Tiberiu Chelcea...
DSD
2007
IEEE
120views Hardware» more  DSD 2007»
14 years 2 months ago
Cotransformation Provides Area and Accuracy Improvement in an HDL Library for LNS Subtraction
The reduction of the cumbersome operations of multiplication, division, and powering to addition, subtraction and multiplication is what makes the Logarithmic Number System (LNS) ...
Panagiotis D. Vouzis, Sylvain Collange, Mark G. Ar...
FPGA
2005
ACM
95views FPGA» more  FPGA 2005»
14 years 1 months ago
The Stratix II logic and routing architecture
This paper describes the Altera Stratix II™ logic and routing architecture. This architecture features a novel adaptive logic module (ALM) that is based on a 6-LUT, but can be p...
David M. Lewis, Elias Ahmed, Gregg Baeckler, Vaugh...
VTS
2006
IEEE
122views Hardware» more  VTS 2006»
14 years 1 months ago
Mixed PLB and Interconnect BIST for FPGAs Without Fault-Free Assumptions
We tackle the problem of fault-free assumptions in current PLB and interconnect built-in-self-test (BIST) techniques for FPGAs. These assumptions were made in order to develop stro...
Vishal Suthar, Shantanu Dutt