Sciweavers

6542 search results - page 1294 / 1309
» The tao of parallelism in algorithms
Sort
View
DAC
2010
ACM
14 years 21 days ago
Off-chip memory bandwidth minimization through cache partitioning for multi-core platforms
We present a methodology for off-chip memory bandwidth minimization through application-driven L2 cache partitioning in multicore systems. A major challenge with multi-core system...
Chenjie Yu, Peter Petrov
ICCD
2007
IEEE
195views Hardware» more  ICCD 2007»
14 years 20 days ago
LEMap: Controlling leakage in large chip-multiprocessor caches via profile-guided virtual address translation
The emerging trend of larger number of cores or processors on a single chip in the server, desktop, and mobile notebook platforms necessarily demands larger amount of on-chip last...
Jugash Chandarlapati, Mainak Chaudhuri
CASES
2006
ACM
14 years 16 days ago
Reaching fast code faster: using modeling for efficient software thread integration on a VLIW DSP
When integrating software threads together to boost performance on a processor with instruction-level parallel processing support, it is rarely clear which code regions should be ...
Won So, Alexander G. Dean
FPGA
2006
ACM
195views FPGA» more  FPGA 2006»
14 years 13 days ago
An adaptive Reed-Solomon errors-and-erasures decoder
The development of Reed-Solomon (RS) codes has allowed for improved data transmission over a variety of communication media. Although Reed-Solomon decoding provides a powerful def...
Lilian Atieno, Jonathan Allen, Dennis Goeckel, Rus...
GECCO
2006
Springer
210views Optimization» more  GECCO 2006»
14 years 13 days ago
Clustering the heap in multi-threaded applications for improved garbage collection
Garbage collection can be a performance bottleneck in large distributed, multi-threaded applications. Applications may produce millions of objects during their lifetimes and may i...
Myra B. Cohen, Shiu Beng Kooi, Witawas Srisa-an
« Prev « First page 1294 / 1309 Last » Next »