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» Thermal modeling and analysis of 3D multi-processor chips
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DATE
2006
IEEE
71views Hardware» more  DATE 2006»
14 years 1 months ago
A logarithmic full-chip thermal analysis algorithm based on multi-layer Green's function
This paper derives the multi-layer heat conduction Green’s function, by integrating the eigen-expansion technique and the classic transmission line theories, and presents a loga...
Baohua Wang, Pinaki Mazumder
CVPR
2007
IEEE
14 years 9 months ago
Thermal-Visible Video Fusion for Moving Target Tracking and Pedestrian Classification
The paper presents a fusion-tracker and pedestrian classifier for color and thermal cameras. The tracker builds a background model as a multi-modal distribution of colors and temp...
Alex Leykin, Yang Ran, Riad I. Hammoud
DAC
2010
ACM
13 years 11 months ago
TSV stress aware timing analysis with applications to 3D-IC layout optimization
As the geometry shrinking faces severe limitations, 3D wafer stacking with through silicon via (TSV) has gained interest for future SOC integration. Since TSV fill material and s...
Jae-Seok Yang, Krit Athikulwongse, Young-Joon Lee,...
CASES
2007
ACM
13 years 11 months ago
Performance optimal processor throttling under thermal constraints
We derive analytically, the performance optimal throttling curve for a processor under thermal constraints for a given task sequence. We found that keeping the chip temperature co...
Ravishankar Rao, Sarma B. K. Vrudhula
CODES
2009
IEEE
14 years 3 days ago
Native MPSoC co-simulation environment for software performance estimation
Performance estimation of Multi-Processor System-On-Chip (MPa high abstraction level is required in order to perform early architecture exploration and accurate design validations...
Patrice Gerin, Mian Muhammad Hamayun, Fréd&...