Sciweavers

572 search results - page 84 / 115
» Threading Software Watermarks
Sort
View
POPL
2009
ACM
14 years 10 months ago
Feedback-directed barrier optimization in a strongly isolated STM
Speed improvements in today's processors have largely been delivered in the form of multiple cores, increasing the importance of ions that ease parallel programming. Software...
Nathan Grasso Bronson, Christos Kozyrakis, Kunle O...
HPCA
2008
IEEE
14 years 10 months ago
Thread-safe dynamic binary translation using transactional memory
Dynamic binary translation (DBT) is a runtime instrumentation technique commonly used to support profiling, optimization, secure execution, and bug detection tools for application...
JaeWoong Chung, Michael Dalton, Hari Kannan, Chris...
ISCA
2008
IEEE
134views Hardware» more  ISCA 2008»
14 years 4 months ago
Flexible Decoupled Transactional Memory Support
A high-concurrency transactional memory (TM) implementation needs to track concurrent accesses, buffer speculative updates, and manage conflicts. We present a system, FlexTM (FLE...
Arrvindh Shriraman, Sandhya Dwarkadas, Michael L. ...
ISPASS
2007
IEEE
14 years 4 months ago
PTLsim: A Cycle Accurate Full System x86-64 Microarchitectural Simulator
In this paper, we introduce PTLsim, a cycle accurate full system x86-64 microprocessor simulator and virtual machine. PTLsim models a modern superscalar out of order x86-64 proces...
Matt T. Yourst
ISPASS
2007
IEEE
14 years 4 months ago
An Analysis of Microarchitecture Vulnerability to Soft Errors on Simultaneous Multithreaded Architectures
Semiconductor transient faults (i.e. soft errors) have become an increasingly important threat to microprocessor reliability. Simultaneous multithreaded (SMT) architectures exploi...
Wangyuan Zhang, Xin Fu, Tao Li, José A. B. ...