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ISCA
2010
IEEE
214views Hardware» more  ISCA 2010»
13 years 9 months ago
Translation caching: skip, don't walk (the page table)
This paper explores the design space of MMU caches that accelerate virtual-to-physical address translation in processor architectures, such as x86-64, that use a radix tree page t...
Thomas W. Barr, Alan L. Cox, Scott Rixner
CIKM
2008
Springer
13 years 9 months ago
Learning a two-stage SVM/CRF sequence classifier
Learning a sequence classifier means learning to predict a sequence of output tags based on a set of input data items. For example, recognizing that a handwritten word is "ca...
Guilherme Hoefel, Charles Elkan
DAC
2006
ACM
13 years 9 months ago
A fast HW/SW FPGA-based thermal emulation framework for multi-processor system-on-chip
With the growing complexity in consumer embedded products and the improvements in process technology, Multi-Processor SystemOn-Chip (MPSoC) architectures have become widespread. T...
David Atienza, Pablo Garcia Del Valle, Giacomo Pac...
CRITICAL
2005
13 years 9 months ago
A manifesto for the performative development of ubiquitous media
This paper addresses design agendas in Human-Computer Interaction and neighbouring fields motivated by the mixing of areas that were mostly kept separate until recently, such as m...
Carlo Jacucci, Giulio Jacucci, Ina Wagner, Thomas ...
DEBS
2008
ACM
13 years 9 months ago
A framework for performance evaluation of complex event processing systems
Several new Complex Event Processing (CEP) engines have been recently released, many of which are intended to be used in performance sensitive scenarios - like fraud detection, tr...
Marcelo R. N. Mendes, Pedro Bizarro, Paulo Marques
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