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DATE
2009
IEEE
111views Hardware» more  DATE 2009»
14 years 5 months ago
Enabling concurrent clock and power gating in an industrial design flow
— Clock-gating and power-gating have proven to be very effective solutions for reducing dynamic and static power, respectively. The two techniques may be coupled in such a way th...
Leticia Maria Veiras Bolzani, Andrea Calimera, Alb...
DATE
2009
IEEE
112views Hardware» more  DATE 2009»
14 years 5 months ago
Package routability- and IR-drop-aware finger/pad assignment in chip-package co-design
—Due to increasing complexity of design interactions between the chip, package and PCB, it is essential to consider them at the same time. Specifically the finger/pad locations...
Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu,...
HOST
2008
IEEE
14 years 4 months ago
Detecting Malicious Inclusions in Secure Hardware: Challenges and Solutions
This paper addresses a new threat to the security of integrated circuits (ICs) used in safety critical, security and military systems. The migration of IC fabrication to low-cost ...
Xiaoxiao Wang, Mohammad Tehranipoor, Jim Plusquell...
DATE
2007
IEEE
112views Hardware» more  DATE 2007»
14 years 4 months ago
Tool-support for the analysis of hybrid systems and models
This paper introduces a method and tool-support for the automatic analysis and verification of hybrid and embedded control systems, whose continuous dynamics are often modelled u...
Andreas Bauer 0002, Markus Pister, Michael Tautsch...
ISQED
2007
IEEE
120views Hardware» more  ISQED 2007»
14 years 4 months ago
Planar-CRX: A Single-Layer Zero Skew Clock Routing in X-Architecture
With its advantages in wirelength reduction and routing flexibility compared with Manhattan routing, X-architecture has been proposed and applied to modern IC design. As a critic...
Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, ...