Sciweavers

1476 search results - page 258 / 296
» Three-dimensional integrated circuits
Sort
View
ITC
2000
IEEE
101views Hardware» more  ITC 2000»
14 years 2 months ago
Which concurrent error detection scheme to choose ?
Concurrent error detection (CED) techniques (based on hardware duplication, parity codes, etc.) are widely used to enhance system dependability. All CED techniques introduce some ...
Subhasish Mitra, Edward J. McCluskey
ISPD
1999
ACM
89views Hardware» more  ISPD 1999»
14 years 2 months ago
VIA design rule consideration in multi-layer maze routing algorithms
—Maze routing algorithms are widely used for finding an optimal path in detailed routing for very large scale integration, printed circuit board and multichip modules In this pap...
Jason Cong, Jie Fang, Kei-Yong Khoo
FPGA
1997
ACM
132views FPGA» more  FPGA 1997»
14 years 2 months ago
Wormhole Run-Time Reconfiguration
Configurable Computing Machines (CCMs) are an emerging class of computing platform which provide the computational performance benefits of ASICs, yet retain the flexibility and ra...
Ray Bittner, Peter M. Athanas
ASPDAC
2007
ACM
140views Hardware» more  ASPDAC 2007»
14 years 2 months ago
An Architecture for Combined Test Data Compression and Abort-on-Fail Test
1 The low throughput at IC (Integrated Circuit) testing is mainly due to the increasing test data volume, which leads to high ATE (Automatic Test Equipment) memory requirements and...
Erik Larsson, Jon Persson
DAC
2007
ACM
14 years 2 months ago
Side-Channel Attack Pitfalls
While cryptographic algorithms are usually strong against mathematical attacks, their practical implementation, both in software and in hardware, opens the door to side-channel at...
Kris Tiri