262 search results - page 39 / 53 » Tilings as a programming exercise |
SC
2009
ACM
14 years 4 months ago
2009
ACM
This paper presents a dynamic task scheduling approach to executing dense linear algebra algorithms on multicore systems (either shared-memory or distributed-memory). We use a tas...
NOCS
2009
IEEE
14 years 4 months ago
2009
IEEE
Future manycore processors will require energyefficient, high-throughput on-chip networks. Siliconphotonics is a promising new interconnect technology which offers lower power, h...
IEEEPACT
2009
IEEE
14 years 4 months ago
2009
IEEE
—Analytical models have been used to estimate optimal values for parameters such as tile sizes in the context of loop nests. However, important algorithms such as fast Fourier tr...
ISHPC
2003
Springer
14 years 3 months ago
2003
Springer
Simultaneous multithreaded processors use shared on-chip caches, which yield better cost-performance ratios. Sharing a cache between simultaneously executing threads causes excessi...
ICS
1999
Tsinghua U.
14 years 2 months ago
1999
Tsinghua U.
Programming languages that provide multidimensional arrays and a flat linear model of memory must implement a mapping between these two domains to order array elements in memory....