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FPL
2003
Springer
95views Hardware» more  FPL 2003»
14 years 3 months ago
A Model for Hardware Realization of Kernel Loops
Abstract. Hardware realization of kernel loops holds the promise of accelerating the overall application performance and is therefore an important part of the synthesis process. In...
Jirong Liao, Weng-Fai Wong, Tulika Mitra
DATE
2000
IEEE
130views Hardware» more  DATE 2000»
14 years 2 months ago
Optimal Hardware Pattern Generation for Functional BIST
∗∗ Functional BIST is a promising solution for self-testing complex digital systems at reduced costs in terms of area and performance degradation. The present paper addresses t...
Silvia Cataldo, Silvia Chiusano, Paolo Prinetto, H...
CHES
2004
Springer
106views Cryptology» more  CHES 2004»
14 years 1 months ago
XTR Implementation on Reconfigurable Hardware
Abstract. Recently, Lenstra and Verheul proposed an efficient cryptosystem called XTR. This system represents elements of F p6 with order dividing p2 -p+1 by their trace over Fp2 ....
Eric Peeters, Michael Neve, Mathieu Ciet
GECCO
2000
Springer
182views Optimization» more  GECCO 2000»
14 years 1 months ago
A Novel Evolvable Hardware Framework for the Evolution of High Performance Digital Circuits
This paper presents a novel evolvable hardware framework for the automated design of digital circuits for high performance applications. The technique evolves circuits correspondi...
Ben I. Hounsell, Tughrul Arslan
EUSFLAT
2003
128views Fuzzy Logic» more  EUSFLAT 2003»
13 years 11 months ago
Hardware implementation of a fuzzy Petri net based on VLSI digital circuits
Industrial processes can be often modelled using Petri nets. If all the process variables (or events) are assumed to be twovalued signals, then it is possible to obtain a hardware...
Jacek Kluska, Zbigniew Hajduk