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DATE
2003
IEEE
120views Hardware» more  DATE 2003»
14 years 4 months ago
Delay Defect Diagnosis Based Upon Statistical Timing Models - The First Step
Abstract — This paper defines a new diagnosis problem for diagnosing delay defects based upon statistical timing models. We illustrate the differences between the delay defect d...
Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-...
ICCAD
2000
IEEE
149views Hardware» more  ICCAD 2000»
14 years 3 months ago
Dynamic Response Time Optimization for SDF Graphs
Synchronous Data Flow (SDF) is a well-known model of computation that is widely used in the control engineering and digital signal processing domains. Existing scheduling methods ...
Dirk Ziegenbein, Jan Uerpmann, Ralph Ernst
DATE
1999
IEEE
80views Hardware» more  DATE 1999»
14 years 3 months ago
Time Constrained Modulo Scheduling with Global Resource Sharing
Commonly used scheduling algorithms in high-level synthesis only accept one process at a time and are not capable of sharing resources across process boundaries. This results in t...
Christoph Jäschke, Rainer Laur, Friedrich Bec...
ISLPED
1997
ACM
96views Hardware» more  ISLPED 1997»
14 years 3 months ago
Re-mapping for low power under tight timing constraints
In this paper1 we propose a novel approach to synthesis for low power under tight timing constraints. Starting from a mapped netlist, we apply a powerful generalized matching algo...
Patrick Vuillod, Luca Benini, Giovanni De Micheli
FPGA
1997
ACM
118views FPGA» more  FPGA 1997»
14 years 2 months ago
Improving Functional Density Through Run-Time Constant Propagation
Circuit specialization techniques such as constant propagation are commonly used to reduce both the hardware resources and cycle time of digital circuits. When recon gurable FPGAs...
Michael J. Wirthlin, Brad L. Hutchings