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ASPDAC
2006
ACM
101views Hardware» more  ASPDAC 2006»
14 years 1 months ago
Worst case execution time analysis for synthesized hardware
- We propose a hardware performance estimation flow for fast design space exploration, based on worst-case execution time analysis algorithms for software analysis. Test cases on s...
Jun-hee Yoo, Xingguang Feng, Kiyoung Choi, Eui-You...
DAC
2001
ACM
14 years 8 months ago
A Framework for Object Oriented Hardware Specification, Verification, and Synthesis
We describe two things. First, we present a uniform framework for object oriented specification and verification of hardware. For this purpose the object oriented language `e'...
Tommy Kuhn, Tobias Oppold, Markus Winterholer, Wol...
CHES
2010
Springer
141views Cryptology» more  CHES 2010»
13 years 8 months ago
Fair and Comprehensive Methodology for Comparing Hardware Performance of Fourteen Round Two SHA-3 Candidates Using FPGAs
Performance in hardware has been demonstrated to be an important factor in the evaluation of candidates for cryptographic standards. Up to now, no consensus exists on how such an e...
Kris Gaj, Ekawat Homsirikamol, Marcin Rogawski
DATE
1999
IEEE
147views Hardware» more  DATE 1999»
13 years 12 months ago
Efficient BIST Hardware Insertion with Low Test Application Time for Synthesized Data Paths
In this paper, new and efficient BIST methodology and BIST hardware insertion algorithms are presented for RTL data paths obtained from high level synthesis. The methodology is ba...
Nicola Nicolici, Bashir M. Al-Hashimi
ICCD
2001
IEEE
112views Hardware» more  ICCD 2001»
14 years 4 months ago
Run-Time Execution of Reconfigurable Hardware in a Java Environment
We present tools that support the runtime execution of applications that mix software running on networks of workstations and reconfigurable hardware. We use JHDL to describe the ...
Laurie A. Smith King, Heather Quinn, Miriam Leeser...