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ASPDAC
2004
ACM
144views Hardware» more  ASPDAC 2004»
14 years 1 months ago
Verification of timed circuits with symbolic delays
When time is incorporated in the specification of discrete systems, the complexity of verification grows exponentially. When the temporal behavior is specified with symbols, the ve...
Robert Clarisó, Jordi Cortadella
IPPS
2003
IEEE
14 years 3 months ago
Better Real-Time Response for Time-Share Scheduling
As computing systems of all types grow in power and complexity, it is common to want to simultaneously execute processes with different timeliness constraints. Many systems use CP...
Scott A. Banachowski, Scott A. Brandt
CODES
1998
IEEE
14 years 2 months ago
A path analysis based partitioning for time constrained embedded systems
The HW/SW partitioning problem addressed in this paper is one of the key steps in the co-design flow of heterogeneous embedded systems. Generally the aim is to provide solutions t...
Luc Bianco, Michel Auguin, Guy Gogniat, Alain Pega...
LATA
2010
Springer
14 years 7 months ago
Verifying Complex Continuous Real-Time Systems with Coinductive CLP(R)
Timed automata has been used as a powerful formalism for specifying, designing, and analyzing real time systems. We consider the generalization of timed automata to Pushdown Timed ...
Neda Saeedloei and Gopal Gupta
ICAPR
2001
Springer
14 years 2 months ago
A Time-Length Constrained Level Building Algorithm for Large Vocabulary Handwritten Word Recognition
In this paper we introduce a constrained Level Building Algorithm (LBA) in order to reduce the search space of a Large Vocabulary Handwritten Word Recognition (LVHWR) system. A ti...
Alessandro L. Koerich, Robert Sabourin, Ching Y. S...