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» Time Management in The High Level Architecture
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VLSID
2002
IEEE
151views VLSI» more  VLSID 2002»
16 years 6 months ago
Mode Selection and Mode-Dependency Modeling for Power-Aware Embedded Systems
Among the many techniques for system-level power management, it is not currently possible to guarantee timing constraints and have a comprehensive system model at the same time. S...
Dexin Li, Pai H. Chou, Nader Bagherzadeh
HPCA
2008
IEEE
16 years 6 months ago
Cluster-level feedback power control for performance optimization
Power control is becoming a key challenge for effectively operating a modern data center. In addition to reducing operating costs, precisely controlling power consumption is an es...
Xiaorui Wang, Ming Chen
EDBT
2004
ACM
108views Database» more  EDBT 2004»
16 years 6 months ago
A Framework for Efficient Storage Security in RDBMS
Abstract. With the widespread use of e-business coupled with the public's awareness of data privacy issues and recent database security related legislations, incorporating sec...
Balakrishna R. Iyer, Sharad Mehrotra, Einar Myklet...
ASPLOS
2009
ACM
16 years 27 days ago
Performance analysis of accelerated image registration using GPGPU
This paper presents a performance analysis of an accelerated 2-D rigid image registration implementation that employs the Compute Unified Device Architecture (CUDA) programming e...
Peter Bui, Jay B. Brockman
GLOBECOM
2009
IEEE
16 years 26 days ago
Development Framework for Implementing FPGA-Based Cognitive Network Nodes
—This paper identifies important features a cognitive radio framework should provide, namely a virtual architecture ware abstraction, an adaptive run-time system for managing co...
Jorg Lotze, Suhaib A. Fahmy, Juanjo Noguera, Baris...