769 search results - page 102 / 154 » Timed Circuit Synthesis Using Implicit Methods |
VLSI
2007
Springer
14 years 4 months ago
2007
Springer
— Software simulation remains the most used method for VHDL RTL functional verification. The functional verification process essentially consists of two parts. The first one is t...
ICCAD
2002
IEEE
14 years 7 months ago
2002
IEEE
We present a new method of built-in-self-test (BIST) for sequential circuits and system-on-a-chip (SOC) using characteristic faults and circuitspecific spectral information in th...
CODES
2007
IEEE
14 years 4 months ago
2007
IEEE
This paper proposes a low power VLIW processor generation method by automatically extracting non-redundant activation conditions of pipeline registers for clock gating. It is impo...
DAC
1999
ACM
14 years 11 months ago
1999
ACM
The advent of portable and high-density devices has made power consumption a critical design concern. In this paper, we address the problem of reducing power consumption via gate-...
VLSID
2007
IEEE
14 years 10 months ago
2007
IEEE
We introduce a novel method of test generation for microprocessors at the RTL using spectral methods. Test vectors are generated for RTL faults, which are the stuck-at faults on i...