769 search results - page 129 / 154 » Timed Circuit Synthesis Using Implicit Methods |
ISPD
1998
ACM
13 years 12 months ago
1998
ACM
As chip size and design density increase, coupling effects (crosstalk) between signal wires become increasingly critical to on–chip timing and even functionality. A method is pr...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
—Verification is a major issue in circuit and system design. Formal methods like bounded model checking (BMC) can guarantee a high quality of the verification. There are severa...
ICCAD
2003
IEEE
14 years 29 days ago
2003
IEEE
The impact of power supply integrity on a design has become a critical issue, not only for functional verification, but also for performance verification. Traditional analysis has...
VRIPHYS
2010
13 years 2 months ago
2010
In this paper, we present a set of methods to improve numerical solvers, as used in real-time non-linear deformable models based on implicit integration schemes. The proposed appr...
ETS
2011
IEEE
12 years 7 months ago
2011
IEEE
Abstract—Networks-on-Chip (NoCs) are implicitly fault tolerant due to their inherent redundancy. They can overcome defective cores, links and switches. As a side effect, yield is...