769 search results - page 18 / 154 » Timed Circuit Synthesis Using Implicit Methods |
GLVLSI
2010
IEEE
14 years 22 days ago
2010
IEEE
Clock skew variations adversely affect timing margins, limiting performance, reducing yield, and may also lead to functional faults. Non-tree clock distribution networks, such as ...
DATE
2005
IEEE
14 years 1 months ago
2005
IEEE
This paper presents the novel idea of multi-placement structures, for a fast and optimized placement instantiation in analog circuit synthesis. These structures need to be generat...
DAC
1999
ACM
14 years 8 months ago
1999
ACM
This paper describes a novel methodology for high performance asynchronous design based on timed circuits and on CAD support for their synthesis using Relative Timing. This method...
CORR
2002
Springer
13 years 7 months ago
2002
Springer
-- This paper introduces a novel method for synthesizing digital circuits derived from Binary Decision Diagrams (BDDs) that can yield to reduction in power dissipation. The power r...
ENGL
2008
13 years 7 months ago
2008
Quantum computer algorithms require an `oracle' as an integral part. An oracle is a reversible quantum Boolean circuit, where the inputs are kept unchanged at the outputs and ...