769 search results - page 21 / 154 » Timed Circuit Synthesis Using Implicit Methods |
ISCAS
2005
IEEE
14 years 1 months ago
2005
IEEE
—As process variations become a significant problem in deep sub-micron technology, a shift from deterministic static timing analysis to statistical static timing analysis for hig...
ICCAD
2001
IEEE
14 years 4 months ago
2001
IEEE
: This paper describes ASF, a novel cell-level analog synthesis framework that can size and bias a given circuit topology subject to a set of performance objectives and a manufactu...
DAC
2006
ACM
14 years 8 months ago
2006
ACM
- Classical two-variable symmetries play an important role in many EDA applications, ranging from logic synthesis to formal verification. This paper proposes a complete circuit-bas...
ICCAD
2007
IEEE
14 years 4 months ago
2007
IEEE
— The research in the field of reversible logic is motivated by its application in low-power design, optical computing and quantum computing. Hence synthesis of reversible logic...
ICCAD
1998
IEEE
13 years 12 months ago
1998
IEEE
This paper presents an efficient statistical design methodology that allows simultaneous sizing for performance and optimization for yield and robustness of analog circuits. The s...