769 search results - page 25 / 154 » Timed Circuit Synthesis Using Implicit Methods |
EH
1999
IEEE
1999
IEEE
Improving Correctness of Finite-State Machine Synthesis from Multiple Partial Input/Output Sequences
13 years 12 months ago
Our previous work focused on the synthesis of sequential circuits based on a partial input/output sequence. As the behavioural description of the target circuit is not known the c...
TVLSI
1998
13 years 7 months ago
1998
— Wave-pipelining is a method of high-performance circuit design which implements pipelining in logic without the use of intermediate latches or registers. The combination of hig...
IOLTS
2008
IEEE
14 years 2 months ago
2008
IEEE
Sets of Pairs of Functions to be Distinguished (SPFD) is a functional flexibility representation method that was recently introduced in the logic synthesis domain, and promises s...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
Conventional high-level synthesis uses the worst case delay to relate all inputs to all outputs of an operation. This is a very conservative approximation of reality, especially i...
ARVLSI
1995
IEEE
13 years 11 months ago
1995
IEEE
Precomputation is a recently proposed logic optimization technique which selectively disables the inputs of a sequential logic circuit, thereby reducing switching activity and pow...