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» Timed Circuit Synthesis Using Implicit Methods
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ITCC
2002
IEEE
14 years 3 months ago
FSM Implementation in Embedded Memory Blocks of Programmable Logic Devices Using Functional Decomposition
: Since modern programmable devices contain embedded memory blocks, there exists a possibility to implement Finite State Machines (FSM) using such blocks. The size of the memory av...
Henry Selvaraj, Mariusz Rawski, Tadeusz Luba
DAC
2000
ACM
14 years 11 months ago
Power minimization using control generated clocks
In this paper we describe an area efficient power minimization scheme "Control Generated ClockingI` that saves significant amounts of power in datapath registers and clock dr...
M. Srikanth Rao, S. K. Nandy
ICCD
2008
IEEE
139views Hardware» more  ICCD 2008»
14 years 7 months ago
Probabilistic error propagation in logic circuits using the Boolean difference calculus
- A gate level probabilistic error propagation model is presented which takes as input the Boolean function of the gate, the signal and error probabilities of the gate inputs, and ...
Nasir Mohyuddin, Ehsan Pakbaznia, Massoud Pedram
IPPS
2005
IEEE
14 years 3 months ago
Designing Scalable FPGA-Based Reduction Circuits Using Pipelined Floating-Point Cores
The use of pipelined floating-point arithmetic cores to create high-performance FPGA-based computational kernels has introduced a new class of problems that do not exist when usi...
Ling Zhuo, Gerald R. Morris, Viktor K. Prasanna
VLSID
1998
IEEE
116views VLSI» more  VLSID 1998»
14 years 2 months ago
Synthesis of Testable RTL Designs
With several commercial tools becoming available, the high-level synthesis of applicationspeci c integrated circuits is nding wide spread acceptance in VLSI industry today. Existi...
C. P. Ravikumar, Sumit Gupta, Akshay Jajoo