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» Timed Circuit Synthesis Using Implicit Methods
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ICCAD
2004
IEEE
80views Hardware» more  ICCAD 2004»
14 years 7 months ago
HiSIM: hierarchical interconnect-centric circuit simulator
To ensure the power and signal integrity of modern VLSI circuits, it is crucial to analyze huge amount of nonlinear devices together with enormous interconnect and even substrate ...
Tsung-Hao Chen, Jeng-Liang Tsai, Tanay Karnik
DATE
2009
IEEE
202views Hardware» more  DATE 2009»
14 years 5 months ago
Design as you see FIT: System-level soft error analysis of sequential circuits
Soft errors in combinational and sequential elements of digital circuits are an increasing concern as a result of technology scaling. Several techniques for gate and latch hardeni...
Daniel Holcomb, Wenchao Li, Sanjit A. Seshia
ICCD
1991
IEEE
65views Hardware» more  ICCD 1991»
14 years 1 months ago
Self-Timed Logic Using Current-Sensing Completion Detection (CSCD)
This article proposes a completion-detection method for efficiently implementing Boolean functions as self-timed logic structures. Current-Sensing Completion Detection, CSCD, allow...
Mark E. Dean, David L. Dill, Mark Horowitz
DATE
2009
IEEE
126views Hardware» more  DATE 2009»
14 years 5 months ago
On hierarchical statistical static timing analysis
— Statistical static timing analysis deals with the increasing variations in manufacturing processes to reduce the pessimism in the worst case timing analysis. Because of the cor...
Bing Li, Ning Chen, Manuel Schmidt, Walter Schneid...
ICIP
2010
IEEE
13 years 8 months ago
Stochastic gradient descent for robust inverse photomask synthesis in optical lithography
Optical lithography is a critical step in the semiconductor manufacturing process, and one key problem is the design of the photomask for a particular circuit pattern, given the o...
Ningning Jia, Edmund Y. Lam