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» Timed Circuit Synthesis Using Implicit Methods
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ICCAD
2007
IEEE
103views Hardware» more  ICCAD 2007»
14 years 7 months ago
Enhancing design robustness with reliability-aware resynthesis and logic simulation
While circuit density and power efficiency increase with each major advance in IC technology, reliability with respect to soft errors tends to decrease. Current solutions to this...
Smita Krishnaswamy, Stephen Plaza, Igor L. Markov,...
ASPDAC
2007
ACM
121views Hardware» more  ASPDAC 2007»
14 years 2 months ago
Timing-Aware Decoupling Capacitance Allocation in Power Distribution Networks
Power supply noise increases the circuit delay, which may lead to performance failure of a design. Decoupling capacitance (decap) addition is effective in reducing the power suppl...
Sanjay Pant, David Blaauw
ITC
2003
IEEE
167views Hardware» more  ITC 2003»
14 years 3 months ago
Path Delay Test Generation for Domino Logic Circuits in the Presence of Crosstalk
A technique to derive test vectors that exercise the worstcase delay effects in a domino circuit in the presence of crosstalk is described. A model for characterizing the delay of...
Rahul Kundu, R. D. (Shawn) Blanton
SAT
2004
Springer
113views Hardware» more  SAT 2004»
14 years 3 months ago
Clause Form Conversions for Boolean Circuits
The Boolean circuits is well established as a data structure for building propositional encodings of problems in preparation for satisfiability solving. The standard method for co...
Paul Jackson, Daniel Sheridan
DATE
2004
IEEE
142views Hardware» more  DATE 2004»
14 years 2 months ago
Eliminating False Positives in Crosstalk Noise Analysis
Noise affects circuit operation by increasing gate delays and causing latches to capture incorrect values. Noise analysis techniques can detect some of such noise faults, but accu...
Yajun Ran, Alex Kondratyev, Yosinori Watanabe, Mal...