Sciweavers

769 search results - page 75 / 154
» Timed Circuit Synthesis Using Implicit Methods
Sort
View
DATE
2008
IEEE
102views Hardware» more  DATE 2008»
14 years 4 months ago
A New Approach for Combining Yield and Performance in Behavioural Models for Analogue Integrated Circuits
A new algorithm is presented that combines performance and variation objectives in a behavioural model for a given analogue circuit topology and process. The tradeoffs between per...
Sawal Ali, Reuben Wilcock, Peter R. Wilson, Andrew...
EMSOFT
2006
Springer
14 years 1 months ago
New approach to architectural synthesis: incorporating QoS constraint
Embedded applications like video decoding, video streaming and those in the network domain, typically have a Quality of Service (QoS) requirement which needs to be met. Apart from...
Harsh Dhand, Basant Kumar Dwivedi, M. Balakrishnan
ICTAI
2002
IEEE
14 years 3 months ago
A Genetic Testing Framework for Digital Integrated Circuits
In order to reduce the time-to-market and simplify gatelevel test generation for digital integrated circuits, GAbased functional test generation techniques are proposed for behavi...
Xiaoming Yu, Alessandro Fin, Franco Fummi, Elizabe...
ITC
2003
IEEE
126views Hardware» more  ITC 2003»
14 years 3 months ago
Diagnosis-Based Post-Silicon Timing Validation Using Statistical Tools and Methodologies
This paper describes a new post-silicon validation problem for diagnosing systematic timing errors. We illustrate the differences between timing validation and the traditional log...
Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, T. M....
DAC
1996
ACM
14 years 2 months ago
A Register File and Scheduling Model for Application Specific Processor Synthesis
In this paper, we outline general design steps of our synthesis tool to realize application specific co-processors such that for a given scientific application having intensive ite...
Ehat Ercanli, Christos A. Papachristou