4306 search results - page 129 / 862 » Timed Testing with TorX |
ISQED
2002
IEEE
14 years 3 months ago
2002
IEEE
This paper presents a hybrid BIST architecture and methods for optimizing it to test systems-on-chip in a cost effective way. The proposed self-test architecture can be implemente...
ITC
2003
IEEE
14 years 3 months ago
2003
IEEE
An early-life reliability model is presented that allows wafer test information to be used to predict not only the total number of burn-in failures that occur for a given product,...
COCO
2000
Springer
14 years 1 months ago
2000
Springer
We consider the problem of testing whether the intersection of a collection of k automata is empty. The straightforward algorithm for solving this problem runs in time k where is...
DATE
2006
IEEE
14 years 4 months ago
2006
IEEE
This paper presents a wrapper and test access mechanism design for multi-clock domain SoCs that consists of cores with different clock frequencies during test. We also propose a t...
ICCD
2004
IEEE
14 years 7 months ago
2004
IEEE
Although scan-based designs are widely used in order to reduce the complexity of test generation, test application time and test data volume are substantially increased. We propos...