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ATS
2003
IEEE
75views Hardware» more  ATS 2003»
14 years 3 months ago
An Enhanced Test Generator for Capacitance Induced Crosstalk Delay Faults
Capacitive crosstalk can give rise to slowdown of signals that can propagate to a circuit output and create a functional error. A test generation methodology, called XGEN, was dev...
Arani Sinha, Sandeep K. Gupta, Melvin A. Breuer
DFT
2005
IEEE
103views VLSI» more  DFT 2005»
14 years 3 months ago
Methodologies and Algorithms for Testing Switch-Based NoC Interconnects
In this paper, we present two novel methodologies for testing the interconnect fabrics of network-on-chip (NoC) based chips. Both use the concept of recursive testing, with differ...
Cristian Grecu, Partha Pratim Pande, Baosheng Wang...
ISCAS
2005
IEEE
100views Hardware» more  ISCAS 2005»
14 years 3 months ago
A test strategy for time-to-digital converters using dynamic element matching and dithering
This work presents a cost-effective test structure that is applicable to built-in self-test of time-to-digital converters (TDCs). The proposed structure uses deterministic dynamic ...
Wenbo Liu, Hanqing Xing, Le Jin, Randall L. Geiger...
RTAS
2011
IEEE
13 years 2 months ago
FPZL Schedulability Analysis
— This paper presents the Fixed Priority until Zero Laxity (FPZL) scheduling algorithm for multiprocessor realtime systems. FPZL is similar to global fixed priority preemptive sc...
Robert I. Davis, Alan Burns
ICCAD
2000
IEEE
124views Hardware» more  ICCAD 2000»
14 years 2 months ago
Deterministic Test Pattern Generation Techniques for Sequential Circuits
This paper presents new test generation techniques for improving the average-case performance of the iterative logic array based deterministic sequential circuit test generation a...
Ilker Hamzaoglu, Janak H. Patel