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ITC
2003
IEEE
205views Hardware» more  ITC 2003»
14 years 3 months ago
H-DFT: A Hybrid DFT Architecture For Low-Cost High Quality Structural Testing
This paper describes a Hybrid DFT (H-DFT) architecture for low-cost, high quality structural testing in the high volume manufacturing (HVM) environment. This structure efficiently...
David M. Wu, Mike Lin, Subhasish Mitra, Kee Sup Ki...
DATE
2005
IEEE
139views Hardware» more  DATE 2005»
14 years 3 months ago
Statistical Timing Analysis with Extended Pseudo-Canonical Timing Model
— State of the art statistical timing analysis (STA) tools often yield less accurate results when timing variables become correlated due to global source of variations and path r...
Lizheng Zhang, Weijen Chen, Yuhen Hu, Charlie Chun...
DATE
2009
IEEE
119views Hardware» more  DATE 2009»
14 years 5 months ago
Improved worst-case response-time calculations by upper-bound conditions
Fast real-time feasibility tests and analysis algorithms are necessary for a high acceptance of the formal techniques by industrial software engineers. This paper presents a possi...
Victor Pollex, Steffen Kollmann, Karsten Albers, F...
DATE
2009
IEEE
138views Hardware» more  DATE 2009»
14 years 5 months ago
Scalable Adaptive Scan (SAS)
Scan compression has emerged as the most successful solution to solve the problem of rising manufacturing test cost. Compression technology is not hierarchical in nature. Hierarch...
Anshuman Chandra, Rohit Kapur, Yasunari Kanzawa
ASPDAC
1995
ACM
66views Hardware» more  ASPDAC 1995»
14 years 1 months ago
Region definition and ordering assignment with the minimization of the number of switchboxes
--In this paper, a region definition and ordering assignment (RDAOA) algorithm on minimizing the number of switchboxes is proposed. The time complexity of the algorithm is proved t...
Jin-Tai Yan