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VLSID
2004
IEEE
139views VLSI» more  VLSID 2004»
14 years 10 months ago
Open Defects Detection within 6T SRAM Cells using a No Write Recovery Test Mode
The detection of all open defects within 6T SRAM cells is always a challenge due to the significant test time requirements. This paper proposes a new design-for-test (DFT) techniq...
André Ivanov, Baosheng Wang, Josh Yang
ICSE
2005
IEEE-ACM
14 years 10 months ago
A framework of greedy methods for constructing interaction test suites
Greedy algorithms for the construction of software interaction test suites are studied. A framework is developed to evaluate a large class of greedy methods that build suites one ...
Charles J. Colbourn, Myra B. Cohen, Renée C...
DFT
2009
IEEE
189views VLSI» more  DFT 2009»
14 years 5 months ago
Analyzing Formal Verification and Testing Efforts of Different Fault Tolerance Mechanisms
Pre-fabrication design verification and post-fabrication chip testing are two important stages in the product realization process. These two stages consume a large part of resourc...
Meng Zhang, Anita Lungu, Daniel J. Sorin
ASPDAC
2009
ACM
262views Hardware» more  ASPDAC 2009»
14 years 4 months ago
Fault modeling and testing of retention flip-flops in low power designs
Low power circuits have become a necessary part in modern designs. Retention flip-flop is one of the most important components in low power designs. Conventional test methodologie...
Bing-Chuan Bai, Augusli Kifli, Chien-Mo James Li, ...
DFT
1998
IEEE
96views VLSI» more  DFT 1998»
14 years 2 months ago
A Systematic Approach for Diagnosing Multiple Delay Faults
In the presence of multiple delay faults, automated diagnostic procedures that make a single fault assumption may give an incorrect diagnosis. In this paper, a systematic approach...
Jayabrata Ghosh-Dastidar, Nur A. Touba