176 search results - page 16 / 36 » Timed Verification of Asynchronous Circuits |
ENTCS
2008
13 years 7 months ago
2008
Given a timed automaton with parametric timings, our objective is to describe a procedure for deriving constraints on the parametric timings in order to ensure that, for each valu...
ACSD
2003
IEEE
14 years 29 days ago
2003
IEEE
Signal Transition Graphs (STGs) are one of the most popular models for the specification of asynchronous circuits. A STG can be implemented if it admits a so-called consistent an...
CHES
2006
Springer
13 years 11 months ago
2006
Springer
Balanced dynamic dual-rail gates and asynchronous circuits have been shown, if implemented correctly, to have natural and efficient resistance to side-channel attacks. Despite thei...
ASYNC
2007
IEEE
14 years 2 months ago
2007
IEEE
A high data rate asynchronous bit-serial link for long-range on-chip communication is presented. The data bit cycle time is equal to a single gate delay, enabling 67Gbps throughpu...
DAC
2004
ACM
14 years 8 months ago
2004
ACM
Current Static Timing Analysis (STA) techniques allow one to verify the timing of a circuit at different process corners which only consider cases where all the supplies are low o...