23 search results - page 1 / 5 » Timing Anomalies in Dynamically Scheduled Microprocessors |
RTSS
1999
IEEE
14 years 3 months ago
1999
IEEE
Previous timing analysis methods have assumed that the worst-case instruction execution time necessarily corresponds to the worst-case behavior. We show that this assumption is wr...
IPPS
1999
IEEE
14 years 3 months ago
1999
IEEE
The rapid progress in high-performance microprocessor design has made it di cult to adapt real-time scheduling results to new models of microprocessor hardware, thus leaving an un...
ISCA
2002
IEEE
14 years 3 months ago
2002
IEEE
The number of pipeline stages separating dynamic instruction scheduling from instruction execution has increased considerably in recent out-of-order microprocessor implementations...
ISCAS
1999
IEEE
14 years 3 months ago
1999
IEEE
The energy usage of computer systems is becoming important, especially for portablebattery-operated applications and embedded systems. A significant reduction in the energy consum...
ISLPED
2005
ACM
14 years 4 months ago
2005
ACM
The instruction scheduling logic used in modern superscalar microprocessors often relies on associative searching of the issue queue entries to dynamically wakeup instructions for...