28 search results - page 4 / 6 » Timing Driven Placement for Quasi Delay-Insensitive Circuits |
ISPD
2007
ACM
13 years 9 months ago
2007
ACM
Traditionally, research in global placement has focused on relatively few simple metrics, such as pure wirelength or routability estimates. However, in the real world today, desig...
DAC
2003
ACM
14 years 21 days ago
2003
ACM
This paper describes a new force directed global placement algorithm that exploits and extends techniques from two leading placers, Force-directed [12] [26] and Mongrel [22]. It c...
FPGA
1998
ACM
13 years 11 months ago
1998
ACM
The goal of this paper is to perform a timing optimization of a circuit described by a network of cells on a target structure whose connection delays have discrete values following...
DAC
2009
ACM
14 years 8 months ago
2009
ACM
As VLSI technology enters the nanoscale regime, interconnect delay has become the bottleneck of the circuit timing. As one of the most powerful techniques for interconnect optimiz...
FPL
2005
Springer
14 years 29 days ago
2005
Springer
This work explores the effect of adding a timing driven functional decomposition step to the traditional field programmable gate array (FPGA) CAD flow. Once placement has comple...